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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. b 11/08/05 issi ? copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. is64wv6416bll is61wv6416bll functional block diagram 64k x 16 high-speed cmos static ram november 2005 features ? high-speed access time: 12 ns: 3.3v + 10% 15 ns: 2.5v-3.6v cmos low power operation: 50 mw (typical) operating 25 w (typical) standby ttl compatible interface levels fully static operation: no clock or refresh required three state outputs data control for upper and lower bytes automotive temperature available lead-free available description the issi is61/64wv6416bll is a high-speed, 1,048,576- bit static ram organized as 65,536 words by 16 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with inno- vative circuit design techniques, yields access times as fast as 12ns (3.3v + 10%) and 15ns (2.5v-3.6v) with low power consumption. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs, ce and oe . the active low write enable ( we ) controls both writing and reading of the memory. a data byte allows upper byte ( ub ) and lower byte ( lb ) access. the is61/64wv6416bll is packaged in the jedec stan- dard 44-pin tsop-ii, and 48-pin mini bga (6mm x 8mm). a0-a15 ce oe we 64k x 16 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll pin configurations 44-pin tsop-ii 48-pin mini bga (6mm x 8mm) pin descriptions a0-a15 address inputs i/o0-i/o15 data inputs/outputs ce chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 nc i/o 8 ub a3 a4 ce i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 nc a7 i/o 3 v dd v dd i/o 12 nc nc i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 nc a8 a9 a10 a11 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a15 a14 a13 a12 a11 ce i/o0 i/o1 i/o2 i/o3 v dd gnd i/o4 i/o5 i/o6 i/o7 we a10 a9 a8 a7 nc a0 a1 a2 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd v dd i/o11 i/o10 i/o9 i/o8 nc a3 a4 a5 a6 nc
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll operating range (v dd ) range ambient temperature v dd (15 ns) v dd (12 ns) commercial 0c to +70c 2.5v-3.6v 3.3v + 10% industrial ?40c to +85c 2.5v-3.6v 3.3v + 10% automotive ?40c to +125c 2.5v-3.6v 3.3v + 10% absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to v dd +0.5 v t stg storage temperature ?65 to +150 c p t power dissipation 1.5 w v dd v dd related to gnd -0.2 to +3.9 v note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table i/o pin mode we we we we we ce ce ce ce ce oe oe oe oe oe lb lb lb lb lb ub ub ub ub ub i/o0-i/o7 i/o8-i/o15 v dd current not selected x h x x x high-z high-z i sb 1 , i sb 2 output disabled h l h x x high-z high-z i cc x l x h h high-z high-z read h l l l h d out high-z i cc h l l h l high-z d out hllll d out d out write l l x l h d in high-z i cc l l x h l high-z d in llxll d in d in
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll dc electrical characteristics (over operating range) v dd = 2.5v-3.6v symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?1.0 ma 2.3 ? v v ol output low voltage v dd = min., i ol = 1.0 ma ? 0.4 v v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd ?2 2 a i lo output leakage gnd v out v dd , outputs disabled ?2 2 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width - 2.0 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width - 2.0 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 3.3v + 10% symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd ?2 2 a i lo output leakage gnd v out v dd , outputs disabled ?2 2 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width - 2.0 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width - 2.0 ns). not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll capacitance (1) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf note: 1. tested initially and after any design or process changes that may affect these parameters. power supply characteristics (1) (over operating range) -12 ns -15 ns symbol parameter test conditions options min. max. min. max. unit i cc v dd dynamic operating v dd = max., com . ?35 ?30 ma supply current i out = 0 ma, f = f max ind . ?45 ?40 auto ?60 ?50 typ. (2) ?20 ?20 i cc 1 operating supply v dd = max., com . ?5 ?5 ma current iout = 0ma, f = 0 ind . ?5 ?5 auto ?5 ?5 i sb 2 cmos standby v dd = max., com . ?20 ?20 ua current (cmos inputs) ce v dd ? 0.2v, ind . ?50 ?50 v in v dd ? 0.2v, or auto ?75 ?75 v in 0.2v, f = 0 typ. (2) ?6 ?6 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd =2.5v, t a =25 o c. not 100% tested.
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll ac test conditions parameter unit unit (2.5v-3.6v) (3.3v + 10%) input pulse level 0v to v dd v 0v to v dd v input rise and fall times 1.5ns 1.5ns input and output timing v dd /2 v dd /2 + 0.05 and reference level (v ref ) output load see figures 1a and 1b see figures 1a and 1b ac test loads figure 1a. figure 1b. 30 pf including jig and scope zo=50 ? output v ref 50 ? 319 ? 5 pf including jig and scope 353 ? output 2.5v
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll read cycle switching characteristics (1) (over operating range) -12 ns -15 ns symbol parameter min. max. min. max. unit t rc read cycle time 12 ? 15 ? ns t aa address access time ? 12 ? 15 ns t oha output hold time 3 ? 3 ? ns t ace ce access time ? 12 ? 15 ns t doe oe access time ? 6 ? 7 ns t hzoe (2) oe to high-z output ? 6 0 6 ns t lzoe (2) oe to low-z output 0 ? 0 ? ns t hzce (2 ce to high-z output 0 6 0 6 ns t lzce (2) ce to low-z output 3 ? 3 ? ns t ba lb , ub access time ? 6 ? 7 ns t hzb lb , ub to high-z output 0 6 0 6 ns t lzb lb , ub to low-z output 0 ? 0 ? ns notes: 1. test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25v, input pulse levels of 0v to v dd v and output loading specified in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested.
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll read cycle no. 2 (1,3) ac waveforms read cycle no. 1 (1,2) (address controlled) ( cs = oe = v il , ub or lb = v il ) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce , ub , or lb = v il . 3. address is valid prior to or coincident with ce low transition. t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid t hzb address oe ce lb , ub d out t hzce t ba t lzb data valid previous data valid t aa t oha t oha t rc d out address
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll write cycle switching characteristics (1,2) (over operating range) -12 ns -15 ns symbol parameter min. max. min. max. unit t wc write cycle time 12 ? 15 ? ns t sce ce to write end 9 ? 10 ? ns t aw address setup time 9 ? 10 ? ns to write end t ha address hold from write end 0 ? 0 ? ns t sa address setup time 0 ? 0 ? ns t pwb lb , ub valid to end of write 9 ? 10 ? ns t pwe 1 we pulse width ( oe = high) 9 ? 10 ? ns t pwe 2 we pulse width ( oe = low) 11 ? 12 ? ns t sd data setup to write end 9 ? 9 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe (3) we low to high-z output ? 6 ? 7 ns t lzwe (3) we high to low-z output 3 ? 3 ? ns notes: 1. test conditions for is61wv6416bll assume signal transition times of 1.5ns or less, timing reference levels of 1.25v, input pulse levels of 0v to v dd v and output loading specified in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write.
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll write cycle no. 1 (1,2) ( ce controlled, oe = high or low) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub , lb we d out d in data in valid t lzwe t sd ub_cewr1.eps
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll write cycle no. 2 (1) ( we controlled, oe = high during write cycle) data undefined low t wc valid address t pwe1 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub , lb we d out d in oe data in valid t lzwe t sd ub_cewr2.eps write cycle no. 3 ( we controlled: oe is low during write cycle) data undefined t wc valid address low low t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub , lb we d out d in oe data in valid t lzwe t sd ub_cewr3.eps
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 ub_cewr4.eps t hd t sa t hzwe address ce ub , lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha write cycle no. 4 ( lb , ub controlled, back-to-back write) (1,3) notes: 1. the internal write time is defined by the overlap of ce = low, ub and/or lb = low, and we = low. all signals must be in valid states to initiate a write, but any can be deasserted to terminate the write. the t sa , t ha , t sd , and t hd timing is referenced to the rising or falling edge of the signal that terminates the write. 2. tested with oe high for a minimum of 4 ns before we = low to place the i/o in a high-z state. 3. we may be held low across many address cycles and the lb , ub pins can be used to control the write function.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll data retention waveform ( ce controlled) data retention switching characteristics symbol parameter test condition operations min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 1.8 ? 3.6 v i dr data retention current v dd = 1.8v, ce v dd ? 0.2v com . ?6 20 a ind . ?6 50 auto ?6 75 t sdr data retention setup time see data retention waveform 0 ? ? ns t rdr recovery time see data retention waveform t rc ?? ns note : 1. typical values are measured at v dd = 2.5v, t a = 25 o c. not 100% tested. v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd 1.65v 1.4v data retention mode
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/08/05 issi ? is64wv6416bll is61wv6416bll ordering information industrial temperature range: ?40c to +85c speed (ns) order part no. package 12 is61wv6416bll-12ti p lastic tsop 12 is61wv6416bll-12tli pl astic tsop, lead-free 12 is61wv6416bll-12bi m ini bga (6mm x 8mm) 12 is61wv6416bll-12bli mini bga (6mm x 8mm), lead-free temperature range (a3): ?40c to +125c speed (ns) order part no. package 15 (12 1 ) is64wv6416bll-15ta3 p lastic tsop 15 (12 1 ) is64wv6416bll-15tla3 pl astic tsop, lead-free 15 (12 1 ) is64wv6416bll-15ba3 m ini bga (6mm x 8mm) 15 (12 1 ) IS64WV6416BLL-15BLA3 mini bga (6mm x 8mm), lead-free note: 1. speed = 12ns for v dd = 3.3v + 10%. speed = 15ns for v dd = 2.5v- 3.6v.
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 01/15/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. mini ball grid array package code: b (48-pin) notes: 1. controlling dimensions are in millimeters. mbga - 6mm x 8mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a 1.20 0.047 a1 0.24 0.30 0.009 0.012 a2 0.60 0.024 d 7.90 8.10 0.311 0.319 d1 5.25 bsc 0.207 bsc e 5.90 6.10 0.232 0.240 e1 3.75 bsc 0.148 bsc e 0.75 bsc 0.030 bsc b 0.30 0.35 0.40 0.012 0.014 0.016 mbga - 8mm x 10mm millimeter inches sym. min. typ. max. min. typ. max. n0. leads 48 a 1.20 0.047 a1 0.24 0.30 0.009 0.012 a2 0.60 0.024 d 9.90 10.10 0.390 0.398 d1 5.25 bsc 0.207 bsc e 7.90 8.10 0.311 0.319 e1 3.75 bsc 0.148 bsc e 0.75 bsc 0.030 bsc b 0.30 0.35 0.40 0.012 0.014 0.016 seating plane a a1 a2 a b c d e f g h e e d1 e1 e d b (48x) top view bottom view 6 5 4 3 2 1 1 2 3 4 5 6 a b c d e f g h
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 06/18/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. plastic tsop package code: t (type ii) d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd . notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max ref. std. no. leads (n) 32 44 50 a ? 1.20 ? 0.047 ? 1.20 ? 0.047 ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 e1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 bsc 0.050 bsc 0.80 bsc 0.032 bsc 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 zd 0.95 ref 0.037 ref 0.81 ref 0.032 ref 0.88 ref 0.035 ref 0 5 0 5 0 5 0 5 0 5 0 5

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